CS代考 DESN2000: Engineering Design & Professional Practice (EE&T) – cscodehelp代写
DESN2000: Engineering Design & Professional Practice (EE&T)
Introduction to embedded systems, ARM architecture and assembly language fundamentals
School of Electrical Engineering & Telecommunications Graduate School of Biomedical Engineering
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Biomedical Microsystems Lab
Why embedded systems?
iPhone Nintendo Switch Network router
Oscilloscope Patient monitors
© 2022 UNSW Sydney
• Dominates the embedded device market (> 95% of smart phones) .
• Increasingly used in PCs (the new Macs) and servers (Amazon).
1 ARMv8.6-A (Nov 2020)
14 ARMv8.5-A (Oct 2020)
© 2022 UNSW Sydney
Technical objectives
• Understanding embedded systems, using ARM architecture as example
• Programming embedded systems
• Interfacing hardware with embedded microprocessors
© 2022 UNSW Sydney
Course staff Course coordinator (Design Next)
School coordinator (EE&T)
Lecturers (Design Next)
Head lab demonstrator (EE&T)
Lab demonstrators (EE&T)
Shiqi (Charlotte) (Tony) Podiono Zachary Sarkar
© 2022 UNSW Sydney
• EE&T: weekly 3-hour lectures, using Blackboard Collaborate (via Moodle).
• Design Next: on some weeks only
• Conservation Biologist Guest Lecture: Week 3, Tuesday 14th June, 1 – 2 PM.
• A biologist’s perspective on bird tracking (your design project).
Centre for Ecosystem Science
School of Biological, Earth and Environmental Sciences (BEES) UNSW
• Lecture is recorded, OK to follow-up after the live lecture. But has Q&A, so attend if you can.
© 2022 UNSW Sydney
EE&T weekly exercises
• Not assessed.
• Answers provided the following week.
• Will announce a weekly consultation to go through some of these (likely Tuesday 12:30-13:00). Will be recorded in Blackboard Collaborate.
• Takes 1 ~ 1.5 hr. DO THEM. FINAL EXAM QUESTIONS ARE SIMILAR TO THESE.
1 Number systems
2 Number systems and ARM architecture
3 Data processing and memory access
4 Control flow
5 Functions
7 I/O interfacing
8 I/O interfacing
9 Pseudo-instructions and directives
© 2022 UNSW Sydney
EE&T laboratory
• 3 hours at ElecEng119 (local students) or online via Teams (overseas students).
• Working in pairs.
• Starts week 3, or week 2 for those in Monday labs (Monday Week-3 is public holiday).
• For remote students: remote access using Teams, webcam, internet-enabled oscilloscopes. Demonstrators will communicate with you using Teams.
Week Contents
2 1 – Introduction to the QVGA base board, μVision and debugging (for students in Mon. labs)
3 1 – Introduction to the QVGA base board, μVision and debugging
4 2.1 – Data types, control flow, assembly programming
5 2.2 – Data types, control flow, assembly programming
6 3 – Functions and subroutines
8 5.1 – D/A conversion
9 5.2 – D/A conversion
10 6 – LCD & touchscreen
© 2022 UNSW Sydney
Assessments
Assessment Contribution
EE&T laboratory exercises 20%
Final exam 30%
Design journal 25%
Design presentation 15%
Code implementation 10%
• EE&T laboratory attendance and exercises are compulsory.
• If you missed your labs, schedule catch-up with
with medical certificate.
• Competing less than 7 of 8 labs = automatic DESN2000 failure, regardless of course
mark. No exception.
© 2022 UNSW Sydney
Getting help
• Fastest: ask your demonstrators during the lab / workshop.
• Moodle Forum actively monitored by lecturers and demonstrators.
• Lab / workshop logistics: (head lab demo;
• Design Next lectures and assessments:
• Elec. lectures and assessments: Dr
Don’t use MS Teams… get buried among the dozens of alerts I get each day.
© 2022 UNSW Sydney
• Introduction to embedded systems
• ARM7TDMI programmer’s model
• ARM instructions and tools
• Assembly language examples
• Assembler directives and operators
© 2022 UNSW Sydney
Embedded systems: introduction
• Traditionally: a microprocessor-based system, having limited resources and
dedicated to a specific task.
• Computers are also microprocessor-based systems but are general purpose devices.
• Embedded systems are typically:
1. Single purpose
2. Cost- and resource-sensitive
3. Real-time constraints
4. Limited by power, speed and area constraints
5. Small code size (a washing machine controller with 16 KB)
© 2022 UNSW Sydney
Embedded systems: types
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e.g. buttons, touch screen
e.g. motors, displays, speaker
Embedded systems: types
e.g. buttons, touch screen
e.g. motors, displays, speaker
Microprocessor-based system
* Microcontroller * CPU-based
* FPGAs – massive (2M logic cells) hardware parallelism
Xilinx Vertex-7
* CPU (ARM Cortex A9) + FPGA (23K logic cells)
Programmable logic devices
System-on-chip (SoC)
© 2022 UNSW Sydney
Embedded systems: microprocessors
The brain of an embedded system is the microprocessor.
A microprocessor has:
Arithmetic Logic Unit (ALU)
Registers and internal bus structure
Control unit (CU) – can be hardwired or microprogrammed
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Embedded systems: microprocessors
• Computation occurs at the transistor level: electrons running around metal traces and semiconductors.
ARM610 processor die photo
• Convenient to have a high-level abstraction.
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ARM7TDMI programmer’s model
In this course:
Applica1ons)and)OS)
High)level)languages)
Instruc1on)Set)Architecture) (ISA))
Microarchitecture)
Transistors)
ARM7TDMI: T: thumb, D: debug, M: multiplier, I: in-circuit emulation © 2022 UNSW Sydney
ARM7TDMI processor architecture Implements ARMv4 instruction set
LPC2478 chip on QVGA board 4 IDE
Assembly language programming
ARM7TDMI programmer’s model
• A description of the ARM7 processor in programmer’s perspective
1. Internal structure: data & control paths
2. Features available: e.g. what registers are accessible and when
3. Exception handling: e.g. how the processor responds to an invalid instruction
• You need to know about the programmer’s model and the instruction set of the underlying architecture to start writing assembly programs.
© 2022 UNSW Sydney
ARM7TDMI processor core
© 2022 UNSW Sydney
THE PROCESSOR (ARM7TDMI)
ARM 7 Thumb On-chip Debug Multiplier Embedded ICE ( In- Circuit Emulation)
ARM7TDMI processor core
THE PROCESSOR (ARM7TDMI)
plier dded
Emulation)
© 2022 UNSW Sydney
ARM7TDMI instructions
• 1st input always comes from the register bank
• 2nd input can be: – Register
– Immediate operand (comes along with the instruction)
– A shifted register value (by barrel shifter)
• Result goes to a register
• Examples:
Output reg Input-1 reg
ADD R1, R1, #0x5
Output reg Input-1 reg
Input-2, an immediate operand
ADD R1, R2, R3, LSL #3
Input-2, a shifted reg
Invalid: cannot shift ALU’s input-1
ADD R1, R2, LSL #2, R3
© 2022 UNSW Sydney
• The caches are managed automatically by the
hardware and effectively invisible to the
application.
Memory hierarchy
Memory hierarchy
Virtual memory is handled by Operating system
On-chip Cache
8-32 Kbytes
A few tens of ns
Hundreds of Kbytes
Main Memory
Mega bytes
Virtual memory (Hard disk)
tens of milliseconds
100 Gbytes
Fast memory is more expensive per bit than slow
Lmowe-mlevoerl (yassembly) programming involves accessing registers and main memory.
Caches are managed automatically by the hardware. Virtual memory is handled by the operating system.
© 2022 UNSW Sydney
Data types
Basic element is a binary digit (a bit).
Bits are organized into:
Byte – 8 bits
Halfword – 16 bits or 2 bytes Word – 32 bits or 4 bytes
ARM instructions are 32 bits wide.
Data is typically handled at word, halfword, and/or byte levels.
Reading or writing data at word level must occur at word-aligned memory addresses, e.g. at 0xXXXXXXX0, 0xXXXXXXX4, 0xXXXXXXX8, 0xXXXXXXXC.
Reading or writing data at halfword level must occur at halfword- aligned memory addresses, e.g. at 0xXXXXXXX0, 0xXXXXXXX2.
© 2022 UNSW Sydney
Main memory
• N-bit address bus ⇒ 2N address space.
fixed number of bits and an address.
• ARM7TDMI has 32-bit address b•usU⇒n2ive=r4sGalBlyofamdeompotreydspwacied.th of each memory
• Organised into groups (e.g. 8 bits).
MEMORY SYSTEM
• Memory can be viewed as group of storage • Each memory location has an address.
• ARM memory contents are 8 bits wide.
elements that hold data, where each elemen
element is 8bits (bytes)
Remember for ARM:
• Memory contents are byte oriented.
• Address bus and data bus are 32-bit wide.
© 2022 UNSW Sydney
Main memory
• Access is limited to load and store operations, between a memory location and a CPU
• Direct memory content manipulation (e.g. adding two variables in the memory) is not
permitted. This is known as a load-store architecture.
• Some CISC (complex instruction set computer) processors have instructions to directly
manipulate contents in the memory. ARM is RISC.
• Example: A+B = C, where A, B and C are variables in memory:
1. Load A and B from memory into register bank, say R0 and R1.
2. Perform the add operation R0 + R1, with result written to, say, R3.
3. Store the result C (in R3) back to memory.
© 2022 UNSW Sydney
Processor modes
PROCESSOR MODES
Why h13ave modes?
processor modes: User, FIQ, IRQ , Supervisor, 1 unprivileAgbedormto,dUe.ndef, and System.
ARM7TDMI has seven processor modes:
• Version 4T (ARM7TDMI) cores support seven 6 privileged modes
Description
Privileged modes/
Exception modes
Supervisor (SVC)
Entered on reset and when a Software Interrupt (SWI) instruction is executed
Entered when a high priority (Fast) interrupt is raised
Entered when a low priority (normal) interrupt is raised
Used to handle memory access violations
Used to handle undefined instructions
Privileged mode using the same registers as User mode
Mode under which most applications/OS tasks run
Unprivileged
© 2022 UNSW Sydney
Basic storage unit of the data path.
32 bits wide (1 word or 4 bytes).
37 physical registers:
30 general purpose registers 6 status registers
1 program counter (PC)
During mode changed, some of the registers are swapped with a set of physically different registers dedicated to the new mode.
At any given time, the programmer can access 15 general purpose registers (r0, r1, …, r14), program counter (PC or r15), and one/two status registers.
USER and SYSTEM share the same register set.
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General purpose registers:
User/System
Supervisor
Interrupt -IRQ
Fast Interrupt – FIQ
R13_ ABORT
R13 _UNDEF
R14_ ABORT
R14 _UNDEF
© 2022 UNSW Sydney
Program counter (PC, R15)
• Program counter is seen by all modes
• Accessible in all modes.
REGISTERS Mode
• Points to the instruction being fetched from memory.
• Inc•remPernotegdrbaym4 acfoteur neatechr iinstsruecetnionbfyetcahl.l modes R15(PC) R15(PC) R15(PC) R15(PC) R15(PC)
User/System Supervisor Abort Undefined Interrupt
Fast Interrupt R15(PC)
User/System
Supervisor
Fast Interrupt
nautn modes.
Supervisor, Abort, Undefined, Interrupt, and Fast Current Program Status Register is seen by all
Current Program Status Register (CPSR)
Interrupt modes have their own Saved Program
Status Register(SPSR) in addition to access to
• Supervisor, Abort, Undefined, Interrupt, and Fast
• Visible in all modes.
• Stores infoCrmPaStiRon,ownhthiechcucrroenmt pmroocnestsorasltaltmus.odes.
Interrupt modes have their own Saved Program
StatusRegister(SMPoSdRe )inadditiontoaccessto
User/System
Supervisor
Fast Interrupt
SPSR_ABORT ode
SPSR _UNDEF
User/System Supervisor CPSR CPSR
CPSR SPSR_ABORT
Undefined CPSR
SPSR _UNDEF
Interrupt CPSR SPSR_ IRQ
Fast Interrupt CPSR
© 2022 UNSW Sydney
Program Status Register
Program status registers
• Both CPSR and SPSR have the following format Program Status Register
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8
Do not modify / Read as Zero
• Bit [7:0] of P
SR r t econtrol • Bit [4:0] of PSRs are called the Mode
The Mode bits
Supervisor mode
Abort mode
Undefined mode
System mode
– N – Negative – Z- Zero
• Bit [31:28] – conditional flags CPSR and SPSR have the same format.
N: neg–atCive- Carry over
Conditional flag bits [31:28]
– V – Overflow C: carry out
• Bit [4:0] – Current Mode V: overflow
• I – IRQ ( disable IRQ if it is set) • F – FIQ ( disable FIQ if it is set)
I: disable IRQs
F: disable FIQs
• T – set to 0 for ARM code ( otherwise THUMB code)
T: ARM Thumb instructions (0 for ARM)
If mode bit pattern that is not valid is r result is unpredictable.
Mode bits [4:0]
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Program counter & 3-stage pipeline
• Dividing a given task into a number of sub-tasks of lower complexity that can be performed in parallel
• Increases real-time throughput.
• ARM7TDMI is a 3-stage pipelined architecture: Fetch, Decode, and Execute.
• During cycle i, instruction pointed to by PC is fetched, while the instruction fetched
during cycle i – 1 is decoded and the instruction decoded during cycle i -1 (i.e.RfeEtchGedISTE
during cycle i – 2) is being executed.
• Upon each fetch, PC is automatically incremented by 4.
• TheARM7TDMI while one instructi being decode, and executed
Execute Decode
© 2022 UNSW Sydney
is a p on is yet a
Instruction
• Exploiting hardware parallelism for increased speed.
Sequential system (one big task)
Parallel system (small tasks)
F = T1 Task2
T1,T2,T3 ⌧T • Newer ARMs have 5-stage pipelines.
F=1 max(T1, T2, T3)
© 2022 UNSW Sydney
ARM instruction set
• ARM instructions are 32 bits.
• Instruction types:
1. Data processing
2. Data transfer
3. Control flow
4. Special
• Instructions have:
MOV, ADD, SUB, ADC, RSB, RSC, MUL,… LDR, STR
MRS, MSR,…
specifies the operation
can be immediate, register, shifted register
• ARM instructions must align to 4-byte boundaries.
© 2022 UNSW Sydney
Assembly code format
• General structure for each line of assembly code:
Assembly examples
Directives
White space
AREA Prog1, CODE, READONLY
Instructions
Label Directives
MOV r0, #x11
MOV r1, r0, LSL #1 MOV r2, r1, LSL #2
; load initial value ; shift 1 bit to left ; shift 1 bit to left
stop B END
For readability: use spaces, not tab character, in your lab assembly code. Comment your code.
© 2022 UNSW Sydney
Assembler directives
• Constants in ARM assembly code: 1. Numeric
If you don’t specify: it is decimal, e.g. 255 Hexadecimal: e.g. 0x255
Any other base: n_xxxx. n is the base (from 2 to 9), xxxx is the number, e.g.
2_10101010
Character: ‘A’
String: “Hello World” (not null-terminated)
• Examples:
MOV R0, #2_10101101 MOV R2, #’B’
• Directives, register names, assembly mnemonics are not case sensitive.
• Precede each line of instruction with space(s). Labels have no preceding space.
© 2022 UNSW Sydney
Assembler directives – AREA
• Defines a block of data or code within your source file. • Syntax:
• section_name is the name of the data or code section. If starting with a digit, it has to be enclosed in bars, e.g. |1_test|
• Optional attributes can be
section_name
> {,attribute} {,attribute} …
• READONLY
• READWRITE
• ALIGN=expr
a section of code, typically declared as read-only. a section of data, can be declared as read-write. declares that the section cannot modified. declares that the section can be modified.
aligns the section into a 2expr-byte boundary.
© 2022 UNSW Sydney
Assembler directives – EQU
• Giving meaningful names to numeric constants in the program. Similar to #define in C.
• name: symbolic name assigned to the constant
• expr can be:
• a 32-bit user defined constant
• an absolute memory address
• a relative memory address
• Examples:
SRAM_BASE EQU 0x40000000 table EQU label+8
; assigns the program-relative 32-bit ; address label+8 to symbol table
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Assembler directives – ENTRY
• Declares an entry point to the program, which must have at least one ENTRY.
• In projects with multiple source files, each source will have an ENTRY directive.
• A single source file should not have more than one ENTRY directive.
• Example:
AREA testprog, CODE, READONLY ENTRY
© 2022 UNSW Sydney
Assembler directives – DCB, DCW, DCD
• Used to declare initial run-time content in the memory at byte-, halfword-, and word- level.
• Allocates and define run-time memory content at byte level.
{label} DCB expr {,expr} …
• label: memory address of the starting byte.
• expr: either a numeric expression that evaluates to an integer in -128 to 255, or a string. For strings, the characters are stored in consecutive lo
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