计算机代写 EEE8087 1 – cscodehelp代写

ACMs − preliminaries
Dr Fei Xia and Dr Alex Bystrov

Prerequisites

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• Petri nets
• State-transition diagrams – Reachabilitygraphs
• Basic understanding of flip-flops, latches, registers and their operations
• Basic understanding of how clock signals are used in computing hardware
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ACM resources
• on “atomic register” and on “asynchronous communication mechanisms”
– Google,IEEExplore,etc.
• Research papers on this subject by the μSystems
Research Group, Newcastle University
– BrowseourpublicationsintheComfortandCoherent projects from
http://async.org.uk/comfort/publications.html and http://async.org.uk/coherent/coherent_publications.html
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Asynchronous Data Communications
• A complex system may include a number of different digital sub-systems, e.g. computers
• A major problem is how to transfer data from one sub-system to another
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Itboilsdowntodatacommunicationsbetweentwo processes, each running on a different digital computation device, e.g. computer
Weviewtheseprocessesasa‘writer’anda‘reader’ and the goal is to transfer data from the writer to the reader correctly and efficiently

Asynchronous Data Communications • Schematic diagram of the data transfer
Computer 1 Writer
Computer 2 Reader
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Fundamental Problem
• Synchronization
– Differentcomputerstendtoberunondifferentclocks
– Butatthebasiclevel,abitofdataissent/received through the smallest memory, i.e. flip-flops or latches
Computer 2
Computer 1
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Fundamental Problem
• Synchronization
– Thelatchesinvolvedneedtobeonthesameclock
– This‘sameclock’needstobetheclockofComputer1 or Computer 2 but these two are not the same!
Computer 2
Computer 1
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Synchronization for data transfer • Synchronizers
– Devicesthatmakethetwosidesofthedatatransfer (writer and reader) run on effectively the same clock
– Losingdatacorrectness
• Problems
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Metastabilitymeansthatfor100%correctnessyou need waiting of unbounded time
Waitingonlyforboundedtimeyouhavenon-zero probabilities of data errors

• Waiting, if unbounded, violates real-time requirements
• Insert a buffer between reader and writer so either side can move on without waiting for the other side?
• Let’s look at the Petri net model of an n-space buffer for asynchronous data communication
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Typical n-space buffers
• First in first out (FIFO)
– Thisisthemostcommonbufferbetweentwo different digital devices
• Last in first out (LIFO)
– Alsoknownasastack,thisislesscommonbetween
two different digital devices
• Random access memory (RAM)
– Generallyknownasabag,ifaccessistrulyrandom there is very little real use for it
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Petri net model of a FIFO buffer • FIFO with n spaces between writer and reader
Writer Reader
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Each space may be empty (E) or full (F)
• The entire buffer may be empty (reader waits) or full (writer waits)
Writer Reader
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• Asynchronous communication mechanism between reader and writer
Writer Reader
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• For fully asynchronous data communication
• No waiting by either writer or reader, single-space buffer
• Wide usage in real-time systems
– Example: public clocks
– ‘Writer’ is the clock’s internal mechanism
– ‘Readers’ are people looking at the clock
– If nobody looks at the clock during an update cycle, it updates anyway – the ‘lost’ value is not used
– If people look at the clock during an update cycle, the ‘data’ stays the same until the next update
– If someone reads the clock multiple times during an update cycle, they read the same value – the same value is re-used
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Full reader/writer asynchrony
• Known by a number of different names, but the same thing conceptually
– : Atomic register https://lamport.azurewebsites.net/pubs/interprocess.ps
– : Pool (four-slot ACM) https://ieeexplore.ieee.org/document/41349
• Writer updates value (overwriting)
• Reader does not modify value (re-reading)
• Buffer always contains one valid data item
– Initialized with valid data value before a run
• Synchronized to the writer when writing, to the reader when reading
– But how to accommodate simultaneous reading/writing?
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ACM preliminaries recap • NoACM
– Fullysynchronizeddatatransfer–readerandwritermust be on the same clock during data transfer and reading and writing happens on the same data at the same time
• Traditional buffers (FIFO etc.)
– Someasynchronyallowedfordatatransfer–readerand writer usually do not access the same data item at the same time
– Waitingcannotbefullyavoided
• Fully asynchronous ACM
– Nowaitingbyeitherside,dataalwaysvalid
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