编程代写 Integrated Electronics & Design – cscodehelp代写
Integrated Electronics & Design
IC Fabrication Techniques
Reading: Chapter 4.0, 4.2, 4.3.1
https://www.xjtlu.edu.cn/en/departments/academic-departments/electrical-and-electronic-engineering/staff/chun-zhao
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IC Fab. Tech. OUTLINE
⚫ ThinFilmFormation
⚫ PhotolithographyandEtching
⚫ IC Resistor
⚫ SheetResistance
⚫ nMOSFET:ProcessFlow
⚫ nMOSFET:Fab.andLayout
⚫ nMOSFET:LayoutRules
Thin film formation
⚫ Thermal oxidation ⚫ CVD
Thermal oxidation
Dry oxidation
Si + O2 → SiO2 (900-1200°C) 700nm oxide: 10 hours (1200°C) Good oxide quality: gate oxide
Wet oxidation
Gate oxide
Si + H2O → SiO2 + 2H2 (900-1200°C)
700nm oxide: 0. 65 hours (1200°C)
Poor oxide quality: field oxide/diffusion barrier (diffusion mask)
Field oxide
Thermal oxidation
Thermal oxidation
Dry oxidation
Si + O2 → SiO2 (900-1200°C) 700nm oxide: 10 hours (1200°C) Good oxide quality: gate oxide
Wet oxidation
Si + H2O → SiO2 + 2H2 (900-1200°C)
700nm oxide: 0. 65 hours (1200°C)
Poor oxide quality: field oxide/diffusion barrier (diffusion mask)
Thermal oxidation
Thermal SiO2 Properties
➢ (1) SiO2 is a good diffusion mask for common dopants
B, P, or As
Diffusion barrier layer (diffusion mask)
➢ (2) Very good etching selectivity between Si and SiO2. SiO2
Thin film formation
⚫ Thermal oxidation ⚫ CVD
Chemical Vapor Deposition (CVD)
⚫ Thin film formation from vapor phase reactants. Deposited films range from metals to semiconductors to insulators.
⚫ An essential process step in the manufacturing of microelectronic devices. High temperatures and low pressures are the most common process conditions, but are not necessary.
⚫ All CVD involves using an energy source to break reactant gases into reactive species for deposition.
Sub-Si (wafer)
SiH4 + O2 → SiO2 + 2H2 gas gas solid
Examples of CVD
⚫ Metals/Conductors – W, Al, Cu,
doped poly-Si
⚫ Insulators (dielectrics) – BPSG,
Si3N4, SiO2
⚫ Semiconductors – Si, Ge, InP, GaAsP
SiCl4 + 2H2 → Si + 4HCl
SiH4 + O2 → SiO2 + 2H2
Thin film formation
⚫ Thermal oxidation ⚫ CVD
Physical Vapor Deposition (PVD)
⚫ No chemical reaction involved ➢ Evaporation
➢ Sputtering
⚫ Usedtoformmetalfilmsormetal oxide films, such as
➢ HfO2 ➢…
Physical Vapor Deposition – Evaporation
Evaporation Al
(Tsource >>Tboiling of Al , 700OC)
Boiling point
H2O: 100oC Al: 660oC
Deposited Al film
Physical Vapor Deposition – Sputtering Al target
Al atoms ejected due to Ar ion bombardment
Ar ions with ~ keV kinetic energy to bomb the Al target
Deposited Al film
Physical Vapor Deposition – Sputtering
oxidation SiO2
Deposited Al film
IC Fab. Tech. OUTLINE
⚫ ThinFilmFormation
⚫ PhotolithographyandEtching
⚫ IC Resistor
⚫ SheetResistance
⚫ nMOSFET:ProcessFlow
⚫ nMOSFET:Fab.andLayout
⚫ nMOSFET:LayoutRules
Photolithography & Etching
⚫ 1:Glassphotomask(mask)
⚫ 2:Applyphotoresist(coating)
⚫ 3: UV exposure
⚫ 4:Development
⚫ 5:Etching
Circuit(电路符号)
Layout(版图)
Photolithographic process
The process of using UV (Ultraviolet) light to transfer patterns from a glass mask onto a surface of the Si wafer.
The photolithographic process
⚫ The process of using UV (Ultraviolet) light to transfer patterns from a glass mask onto a surface of the Si wafer.
1. Glass Photomask (mask)
Opaque Region (chromium)
Translucent Region
• One mask for each lithography level in process
Photolithography & Etching
⚫ 1:Glassphotomask(mask)
⚫ 2:Applyphotoresist(coating)
⚫ 3: UV exposure
⚫ 4:Development
⚫ 5:Etching
Spin coating process:
A controlled volume of photoresist is dispensed onto a wafer
The wafer is spun at high speed to produce a uniform photoresist film.
2. Coating
Using the mask
Preparing the surface: Grow a thin layer of SiO2
Apply on top of the SiO2 layer a
negative photoresist (PR1);
thickness around 1 μm
Place a mask (M1) in close proximity of the wafer
Spin photoresist
Photolithography & Etching
⚫ 1:Glassphotomask(mask)
⚫ 2:Applyphotoresist(coating)
⚫ 3: UV exposure
⚫ 4:Development
⚫ 5:Etching
3. UV exposure
Ultraviolet Light source
⚫ After placing M1 in close proximity of the wafer, an project UV light through the mask into PR1;
⚫ Induce changes in the polymer structure and these regions will be insoluble to an organic solvent.
⚫ The regions where the mask was opaque will not be exposed.
Photolithography & Etching
⚫ 1:Glassphotomask(mask)
⚫ 2:Applyphotoresist(coating)
⚫ 3: UV exposure
⚫ 4:Development
⚫ 5:Etching
4. Development (negative resist)
insoluble to an organic solvent.
The exposed regions will be
The regions, which is not exposed, will be soluble to an organic solvent
Process of Development
Process steps
3.UV exp 1. thin film
2. coating 4. develop
Photolithography & Etching
⚫ 1:Glassphotomask(mask)
⚫ 2:Applyphotoresist(coating)
⚫ 3: UV exposure
⚫ 4:Development
⚫ 5:Etching
5. Etching
Wet Etching
SiO2 + 6HF → H2SiF6+2H2O (acid solution)
Dry Etching
REI (e.g. CF4 plasma)
Etching PR removing
Photoresist
Positive Resist: Part exposed to light will be dissolved in development solution. Negative Resist: …will not be…
(clear field)
Part exposed to light will be dissolved in development solution
Positive Photoresist
Mask (dark field)
Part exposed to light will not be dissolved in development solution
Negative Photoresist
Example 1: negative photoresist Hardened
photoresist
Exposed photoresist becomes insoluble
Example 2: positive photoresist
Deposited Film:
SiO2, Si3N4, Al, Cu, Poly-Si……
Insoluble photoresist
Exposed photoresist becomes soluble
IC Fab. Tech. OUTLINE
⚫ ThinFilmFormation
⚫ PhotolithographyandEtching
⚫ IC Resistor
⚫ SheetResistance
⚫ nMOSFET:ProcessFlow
⚫ nMOSFET:Fab.andLayout
⚫ nMOSFET:LayoutRules
⚫ Thermal Diffusion ⚫ Ion Implantation
Intrinsic Semiconductor
Silicon has four valence electrons
⚫ It covalently bonds with 4 adjacent atoms in the crystal lattice
⚫ Increasing Temperature Causes Creation of Free Carriers. 1010cm-3 free carriers at 23oC (out of 2x1023cm-3): Intrinsic Conductivity.
outmost orbit: 4 valence electrons
Intrinsic Semiconductor
Covalent Bond
: shared electrons
The Doping
⚫ The addition of a small percentage of foreign atoms in the regular crystal lattice of silicon or germanium produces dramatic changes in their electrical properties, producing n- type and p-type semiconductors.
Element periodic table
Column V elements are Doping (N type) donors, e.g. P, As, Sb
By substituting a Si atom with a special impurity atom (Column V
element), a conduction electron is created.
Donors: P, As, Sb
Phosphorus has 5 valence electrons
⚫ ‘Donates’ one conduction electron to lattice
⚫ Our substrate has 1015cm-3 phosphorus (1 in 108)
Column III elements are Doping (P type) acceptors, e.g. B, Al, Ga
By substituting a Si atom with a special impurity atom (Column III
element), a conduction hole is created.
Acceptors: B, Al, Ga, In
Boron has 3 valence electrons
⚫ ‘Accepts’ one electron from lattice
⚫ Creates a ‘hole’
⚫ Diffusion is the movement of one material through another from a region of relatively higher concentration into a region of lower concentration. There are two steps to thermal diffusion:
➢ Pre-deposition ➢ Drive-in
⚫ Dopant Diffusion Sources ➢ Gas Source: AsH3, PH3, B2H6
B2H6 or PH3
Diffusion mask
Diffusion mask
B2H6 or PH3
Thermal Diffusion Example
Yellow region ND=1015/cm3, NSi=5×1022/cm3
Green region
Thermal Diffusion Example
n-type ND=1019/cm3
p-type NA=1017/cm3
ND=1015/cm3
ND=1019/cm3
Brown region
NA=1017/cm3
Green region
Ion Implantation
As+ with kinetic energy
Implantation causes
(1) damaged region
-substitutional location
Green region n-type
Annealing (Drive-in)
Implantation causes
(1) damaged region and disorder cluster
To activate the implanted ions and to restore material properties, the semiconductor must be annealed.
-substitutional location
Next week:
Fab. Tech. examples
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