CS代写 16. Please list the 4 types of kernels that we discussed in class. For each – cscodehelp代写
16. Please list the 4 types of kernels that we discussed in class. For each, please give an example of OS/paper using that type of kernel design. (Restrict your answer in 30 words total.) — 12%
Monolithic: Old UNIX
Microkernel: Mach/Nucleus
Modular: Linux/Windows/MacOS X
Layered: THE
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17. What is “saturation”? What is “thrashing”? What phenomenon will happen when each occurs? (30 words total) — 8%
Saturation: when the system overcommitted its own processing resources (2%)
Thrashing: when the system overcommitted its own memory resources (2%)
When saturation occurs, the system will spend most of time performing context switches without making progress in computation (2%)
When Thrashing occurs, the system will spend most of time swapping memory pages without making reasonable progress. (2%)
18. Corbato et. al. proposed a “multi-level scheduling algorithm” in their “an experimental time- sharing system”. According to this description, can you describe three guidelines of this policy? — 12%
1. Giving smaller tasks higher priority
2. Giving new tasks higher priority
3. Giving larger tasks longer scheduling quanta to reduce the context switch overhead (4% each)
19. Please list at least four things that will occur during a context switch. Then, consider a machine using 3.6GHz intel Core i7-9700 Processor with 32 GB memory.. Please make an estimation of the context switching overhead on this machine — in terms of orders of magnitude (e.g. nanoseconds, microseconds, milliseconds, seconds… ). Please justify your answers with some latency numbers we learned from the class. — 12%
When happens during a context switch: (8% if you have four of them. Deduct 2% if anything not occur during context switch is listed.)
1. Save the current CPU states in the PCB/task_struct
2. Set the process state from running to ready
3. Invalidate cache
4. Invalidate TLB
5. Load the PCB/task_struct of the target process/task
6. Load the root page table node to the main memory
7. Set the PTBR/CR3 to the page table of the process
8. Set the PC of the target process/task (You don’t have to load the whole program content of the target process
It would take a total of several microseconds. (4%)
Because — among these steps, 1., 5., 6, would require accesses to memory that may lead to TLB misses or even disk accesses. Each memory access take at least 100 ns, a TLB miss takes at least 500 ns to go through x86’s hierarchical page table (4%).
20. Assume the system has installed physical memory that can only accommodate 3 pages at the same time. Consider the following virtual memory page access sequence: 1, 2, 1, 2, 3, 4, 1, 2, 3, 4, 5, 6 Comparing using FIFO and Clock policies when page replacement occurs, which policy would perform better? Write down your answer and justify it. (You may not need to illustrate all page faults in both schemes) — 8%
Clock performs better as it always keeps 1, 2 after the first two page faults on them.
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