程序代写代做代考 x86 chain file system mips cache database PowerPoint 演示文稿

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CO101
Principle of Computer

Organization
Lecture 19: IO System

Liang Yanyan

澳門科技大學
Macau of University of Science and

Technology

Review: Major Components of a Computer

Processor

Control

Datapath

Memory

Devices

Input

Output

A Typical I/O System

Processor

Cache

Memory – I/O Bus

Main
Memory

I/O
Controller

Disk

I/O
Controller

Graphics Network

Interrupts

Disk

Input and Output Devices
• I/O devices are incredibly diverse with respect to

• Behavior – input, output or storage
• Partner – human or machine
• Data rate – the peak rate at which data can be transferred

between the I/O device and the main memory or processor

Device Behavior Partner Data rate (Mb/s)
Keyboard input human 0.0001
Mouse input human 0.0038
Laser printer output human 3.2000
Magnetic disk storage machine 800.0000-3000.0000
Graphics display output human 800.0000-8000.0000
Network/LAN input or

output
machine 100.0000-10000.0000

8 orders of m
agnitude

range

Important metrics for an I/O system
• Dependability
• Performance
• Expandability
• Cost, size, weight
• Security

I/O System Characteristics
• Dependability is important

• Particularly for storage devices
• Performance measures

• Latency (response time)
• Throughput (bandwidth)
• Desktops & embedded systems

• Mainly interested in response time & diversity of devices
• Servers

• Mainly interested in throughput & expandability of devices

I/O Performance Measures
• I/O bandwidth (throughput) – amount of information that

can be input (output) and communicated across an
interconnect (e.g., a bus) to the processor/memory (I/O
device) per unit time
1. How much data can we move through the system in a certain

time?
2. How many I/O operations can we do per unit time?

• I/O response time (latency) – the total elapsed time to

accomplish an input or output operation
• An especially important performance metric in real-time

systems

• Many applications require both high throughput and
short response times

Bus
• A bus is a shared communication link (a single set of

wires used to connect multiple subsystems) that needs
to support a range of devices with widely varying
latencies and data transfer rates
• Advantages

• Versatile – new devices can be added easily and can be moved
between computer systems that use the same bus standard

• Low cost – a single set of wires is shared in multiple ways
• Disadvantages

• Creates a communication bottleneck – bus bandwidth limits the
maximum I/O throughput

• The maximum bus speed is largely limited by
• The length of the bus
• The number of devices on the bus

Types of Buses
• Processor-memory bus (“Front Side Bus”, proprietary)

• Short and high speed
• Matched to the memory system to maximize the memory-

processor bandwidth
• Optimized for cache block transfers

• I/O bus (industry standard, e.g., SCSI, USB, Firewire)
• Usually is lengthy and slower
• Needs to accommodate a wide range of I/O devices
• Use either the processor-memory bus or a backplane bus to

connect to memory
• Backplane bus (industry standard, e.g., ATA, PCIexpress)

• Allow processor, memory and I/O devices to coexist on a single
bus

• Used as an intermediary bus connecting I/O busses to the
processor-memory bus

I/O Transactions
• An I/O transaction is a sequence of operations over the

interconnect that includes a request and may include a
response either of which may carry data.

• A transaction is initiated by a single request and may
take many individual bus operations. An I/O transaction
typically includes two parts

1. Sending the address
2. Receiving or sending the data

• Bus transactions are defined by what they do to memory

• A read transaction reads data from memory (to either the
processor or an I/O device)

• A write transaction writes data to the memory (from either the
processor or an I/O device)

Synchronous and Asynchronous Buses
• Synchronous bus (e.g., processor-memory buses)

• Includes a clock in the control lines and has a fixed protocol for
communication that is relative to the clock

• Advantage: involves very little logic and can run very fast
• Disadvantages:

• Every device communicating on the bus must use same clock rate
• To avoid clock skew, they cannot be long if they are fast

• Asynchronous bus (e.g., I/O buses)
• It is not clocked, so requires a handshaking protocol and

additional control lines (ReadReq, Ack, DataRdy)
• Advantages:

• Can accommodate a wide range of devices and device speeds
• Can be lengthened without worrying about clock skew or

synchronization problems
• Disadvantage: extra synchronous overhead, slow(er)

Advanced Technology Attachment (ATA) Cable

• Backplane bus
• Connects hard drives, CD-ROM drives, and other drives
• [Old] Parallel ATA (PATA): synchronous

Asynchronous Bus Handshaking Protocol
• Output (read) data from memory to an I/O device

13
7. I/O device sees DataRdy go low and drops Ack

I/O device signals a request by raising ReadReq and putting the addr on the
data lines

1
2

ReadReq

Data

Ack

DataRdy

addr data

5
6

1. Memory sees ReadReq, reads addr from data lines, and raises Ack
2. I/O device sees Ack and releases the ReadReq and data lines
3. Memory sees ReadReq go low and drops Ack
4. When memory has data ready, it places it on data lines and raises DataRdy
5. I/O device sees DataRdy, reads the data from data lines, and raises Ack
6. Memory sees Ack, releases the data lines, and drops DataRdy

I/O Bus Examples

Firewire USB 2.0 PCI Express Serial ATA Serial
Attached
SCSI

Intended use External External Internal Internal External
Devices per
channel

63 127 1 1 4

Data width 4 2 2/lane 4 4
Peak
bandwidth

50MB/s or
100MB/s

0.2MB/s,
1.5MB/s, or
60MB/s

250MB/s/lane
1×, 2×, 4×,
8×, 16×,
32×

300MB/s 300MB/s

Hot pluggable Yes Yes Depends Yes Yes

Max length 4.5m 5m 0.5m 1m 8m
Standard IEEE 1394 USB

Implementers
Forum

PCI-SIG SATA-IO INCITS TC
T10

A Typical I/O System

Memory
Controller

Hub
(north bridge)

5000P

Intel Xeon 5300
processor

Main
memory
DIMMs

Front Side Bus
(1333MHz, 10.5GB/sec) FB DDR2 667

(5.3GB/sec)

PCIe 8x (2GB/sec) ESI (2GB/sec)

I/O

Controller
Hub

(south bridge)
Entreprise

South
Bridge 2

CD/DVD

Disk

Disk Serial ATA
(300MB/sec)

Keyboard,
Mouse, …

LPC
(1MB/sec)

USB ports USB 2.0
(60MB/sec)

PCIe 4x
(1GB/sec)
PCIe 4x

(1GB/sec)
PCI-X bus
(1GB/sec)
PCI-X bus
(1GB/sec)

Parallel ATA
(100MB/sec)

Several other tasks
• This still leaves several other tasks that must be

performed to actually cause data to be
transferred from a device and into the memory
address space of some user program.
• How is a user I/O request transformed into a device

command and communicated to the device?
• How is data actually transferred to or from a memory

location?
• What is the role of the operating system?

I/O Management
• I/O is mediated by the OS that acts as the interface

between the I/O hardware and the program requesting
I/O since
• Multiple programs share I/O resources

• Need protection and scheduling
• I/O systems often use interrupts (externally generated

exceptions) to communicate information about I/O operations
• Same mechanism as exceptions

• I/O programming is fiddly, Low-level control of an I/O device is
complex and detailed

• OS provides abstractions to programs

Interfacing I/O Devices to the
Processor, Memory, and OS
• Thus OS must

• guarantee that a user’s program accesses only the portions of
an I/O device to which the user has rights

• provide abstractions for accessing devices by supplying routines
that handle low-level device operations

• Handle the interrupts generated by I/O devices
• provide equitable access to the shared I/O resources
• schedule I/O requests to enhance system throughput

Interfacing I/O Devices to the
Processor, Memory, and OS
• To perform these functions on behalf of user programs,

the operating system must be able to communicate with
the I/O devices and to prevent the user program from
communicating with the I/O devices directly. Three types
of communication are required
• OS must be able to give commands to the I/O devices
• The device must be able to notify the OS when the I/O device

has completed an operation or has encountered an error
• Data must be transferred between memory and an I/O device

How Processor Ditects I/O Devices
• Port-mapped I/O (PMIO)

• special class of CPU instructions for performing I/O
• EX: in and out instructions in x86 architecture

• Memory-mapped I/O (MMIO)
• Portions of the high-order memory address space are assigned

to each I/O device
• Read and writes to those memory addresses are interpreted as

commands to the I/O devices
• Load/stores to the I/O address space can only be done by the

OS
• EX: MIPS

How I/O Devices Communicate
with Processor
Polling
• Periodically check I/O status register

• If device ready, do operation
• If error, take action

• Common in small or low-performance real-time
embedded systems
• Predictable timing
• Low hardware cost

• In other systems, wastes CPU time

How I/O Devices Communicate
with Processor
Interrupts
• When a device is ready or error occurs

• Controller interrupts CPU
• Interrupt is like an exception

• But not synchronized to instruction execution
• Can invoke handler between instructions
• Cause information often identifies the interrupting device

• Priority interrupts
• Devices needing more urgent attention get higher priority
• Can interrupt handler for a lower priority interrupt

Interrupt Driven I/O
• Asynchronous

• does NOT prevent any instruction from completing
• Need a way to identify the device generating the interrupt
• Can have different urgencies (so need a way to prioritize them)

• Advantages
• Relieves the processor from having to continuously polling
• user program progress is only suspended during the actual

transfer of
• I/O data to/from user memory space

• Disadvantage
• need special hardware support

Direct Memory Access (DMA)
• For high-bandwidth devices (like disks) interrupt-driven I/O would

consume a lot of processor cycles

• With DMA, the DMA controller has the ability to transfer large blocks
of data directly to/from the memory without involving the processor

• The processor initiates the DMA transfer by supplying the I/O device
address, the operation to be performed, the memory address
destination/source, the number of bytes to transfer

• The DMA controller manages the entire transfer (possibly thousand
of bytes in length), arbitrating for the bus

• When the DMA transfer is complete, the DMA controller interrupts
the processor to let it know that the transfer is complete

• There may be multiple DMA devices in one system Processor and
DMA controllers contend for bus cycles and for memory

DMA Example

DMA & Virtual Memory Considerations
• Should the DMA work with virtual addresses or physical

addresses?
• If with Physical Address:

• Must constrain all of the DMA transfers to stay within one page
because if it crosses a page boundary, then it wont necessarily be
contiguous in memory

• If the transfer won’t fit in a single page, it can be broken into a series
of transfers (each of which fit in a page) which are handled
individually and chained together

• If with virtual Address:
• The DMA controller will have to translate the virtual address to a

physical address (i.e., will need a TLB structure)
• Whichever is used, the OS must cooperate by not remapping

pages while a DMA transfer involving that page is in progress.
Otherwise, may cause Coherency problem.

Measuring I/O Performance
• I/O performance depends on

• Hardware: CPU, memory, controllers, buses
• Software: operating system, database management system,

application
• Workload: request rates and patterns

• I/O system design can trade-off between response time
and throughput
• Measurements of throughput often done with constrained

response-time

File System & Web Benchmarks
• SPEC System File System (SFS)

• Synthetic workload for NFS server, based on monitoring real
systems

• Results
• Throughput (operations/sec)
• Response time (average ms/operation)

• SPEC Web Server benchmark
• Measures simultaneous user sessions, subject to required

throughput/session
• Three workloads: Banking, Ecommerce, and Support

CO101�Principle of Computer Organization
Review: Major Components of a Computer
A Typical I/O System
Input and Output Devices
Important metrics for an I/O system
I/O System Characteristics
I/O Performance Measures
Bus
Types of Buses
I/O Transactions
Synchronous and Asynchronous Buses
Advanced Technology Attachment (ATA) Cable
Asynchronous Bus Handshaking Protocol
I/O Bus Examples
A Typical I/O System
Several other tasks
I/O Management
Interfacing I/O Devices to the Processor, Memory, and OS
Interfacing I/O Devices to the Processor, Memory, and OS
How Processor Ditects I/O Devices
How I/O Devices Communicate with Processor
How I/O Devices Communicate with Processor
Interrupt Driven I/O
Direct Memory Access (DMA)
DMA Example
DMA & Virtual Memory Considerations
Measuring I/O Performance
File System & Web Benchmarks

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