程序代做CS代考 data structure compiler assembly Compiler Design Week 9 – cscodehelp代写
Compiler Design Week 9
Detailed content
Weekly program
Week Week Week Week Week Week Week Week
Week
Week Week Week Week
1 – Introduction to Compiler Design 2 – Lexical Analysis
3 – CD Programming Language
4 – Syntax Analysis
5 – Top Down Parsing
6 – Symbol Table and Error Recovery 7 – Bottom-Up Parsing
8 – Semantic Analysis
9 – Run-Time Environment: Stack Machine (SM) Architecture
10 – Code Generation
11 – Code Optimisation
12 – Revision
13 – Extra revision (if needed)
2
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Week 09 Lecture Outline
Run-Time Environment: Stack Machin Architecture
Runtime Environment
Zero Address vs 1, 2, 3 Address Machines
Basic Structure of our Stack Machine Stack Machine Architecture
SM Assembly Level Instructions
Variable Allocation and Accessing
Array Allocation and Accessing
Procedure/Function Activation
3
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Run-Time Environment
• A Compiler must accurately implement the source language abstractions:
– Names, scopes, data types, operators, procedures, parameters, control structures etc.
• Cooperates with OS to support these abstractions on the target machines
• Run-time environment deals with
– Layout and allocation of storage locations for the object names
– Mechanism of accessing variables
– Linkages between procedures
– Mechanism for passing parameters
– Interface to OS, input/output devices and other programs
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Storage Organization
• Compiler’s perspective:
– each program runs in its own logical address space and
– each program value has a location
• Organization and management of the logical address space is shared between Compiler, OS and target machine
• Typical assumptions
– Run-time memory is based on contiguous bytes
– The smaller addressed space is a byte (4 bytes = word)
– The number of bytes for a data depends on its type
– Storage layout is strongly influenced by the addressing constraints of the target machine
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Storage Organization
• The space (in bytes) required for the Code is calculated at compile
time.
• Some program data (e.g. global constants and data generated by
compiler) known at compile time and put in Static area
• Stack is used to store activation records
– Data structure required for procedure calls • Heap is to store dynamically allocated data
Code
Static
Stack
Free Memory
Heap
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Run-time Environment for COMP3290
• Stack Machine Simulator
• Stack machine (SM) is a 0-address machine.
• SM
• We
only has a stack and a static area.
will need to convert
– High level CD20 language features (functions, structures, etc.) into
– Low level SM20 operations (arithmetic, data movement, control
jumps)
will look into
• We
– Where the variables live?
– Where the constants stored?
– What do structures look like in memory?
– What do functions look like in memory?
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n-Address Machines
• • •
3 Address: ADD 2 Address: MOV
a, b, c // c := b + a;
// load, operation and store in one instruction
// c:=b;
// c:=c+a;
// ACC := a;
// ACC := ACC + b; // c := ACC;
1 Address: GET ADD b
b, c ADD a,c
a STO c
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n-Address Machines
• 0 Address: PUSH a
// STACK := a , as before;
// STACK := b, a , as before;
// STACK := (b+a) , as before;
// c := STACK, STACK := as before
PUSH ADD POP
b c
….
….
a
….
a
b
….
b+a
….
PUSH a
PUSH b
ADD POP c
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SM – Basic Structure
• A byte address-able, zero-address machine
• Addresses are 32 bits
– Memory capacity is 232 bytes (4GB)
• Memory is organised into 64 bit words (capacity 229 words)
• Any address can be divided into 2 parts
– the word numbertop 29 bits
– the byte numberbottom 3 bits
• Even though memory is byte addressable we can only read and write words into/out of memory.
– ie. Words must be on a word boundary.
• The memory address register (MAR) is 29 bits (a word no.).
• Instructions are 1, 2, 3 or 5 bytes long.
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Address
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000001 00000000 00000000 00000000 00000010 00000000 00000000 00000000 00000011 00000000 00000000 00000000 00000100 00000000 00000000 00000000 00000101 00000000 00000000 00000000 00000110 00000000 00000000 00000000 00000111 00000000 00000000 00000000 00001000 00000000 00000000 00000000 00001001 00000000 00000000 00000000 00001010 00000000 00000000 00000000 00001011 00000000 00000000 00000000 00001100 00000000 00000000 00000000 00001101 00000000 00000000 00000000 00001110 00000000 00000000 00000000 00001111 00000000 00000000 00000000 00010000 00000000 00000000 00000000 00010001 00000000 00000000 00000000 00010010 00000000 00000000 00000000 00010011
….
Memory
…
10
SM – Basic Structure
Processor
Memory
wb PC
IB 0 1 2 3 4 5 6 7
01234 IR
29
3
8
8
8
8
8
8
8
8
8
8
8
8
8
MAR
MDR
64
read write
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14
11
SM – Microcode (A)
• Basic read and write of memory
• READ:
• WRITE:
MAR := Address.w
read;
Data is in MDR, can transfer to a register.
MDR := Data
MAR := Address.w
write;
Data is stored at the given address.
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SM – Cycle
Processor
Memory
wb
29 3
PC
IB 0 1 2 3 4 5 6 7
01234 IR
0000000000
0000000000
111111111
000
XXXYYZZZ ZZAAABBC
MAR (29)
MDR
64
read write
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0000000000
14
0000000000
111111111
13
SM – Cycle
Processor
Memory
wb
29 3
PC
IB 0 1 2 3 4 5 6 7
01234 IR
0000000000
0000000000
111111111
000
X
X
X
Y
Y
Z
Z
Z
XXXYYZZZ ZZAAABBC
MAR (29)
MDR
64
read write
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0000000000
14
0000000000
111111111
14
SM – Cycle
Processor
Memory
wb
29 3
PC
IB 0 1 2 3 4 5 6 7
01234 IR
0000000000
0000000000
111111111
011
X
X
X
Y
Y
Z
Z
Z
X
X
X
XXXYYZZZ ZZAAABBC
MAR (29)
MDR
64
read write
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0000000000
14
0000000000
111111111
15
SM – Cycle
Processor
Memory
wb
29 3
PC
IB 0 1 2 3 4 5 6 7
01234 IR
0000000000
0000000000
111111111
101
X
X
X
Y
Y
Z
Z
Z
Y
Y
XXXYYZZZ ZZAAABBC
MAR (29)
MDR
64
read write
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0000000000
14
0000000000
111111111
16
SM – Cycle
Processor
Memory
wb
29 3
PC
IB 0 1 2 3 4 5 6 7
01234 IR
0000000000
0000000000
111111111
111
X
X
X
Y
Y
Z
Z
Z
Z
Z
Z
XXXYYZZZ ZZAAABBC
MAR (29)
MDR
64
read write
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0000000000
14
0000000000
111111111
17
SM – Cycle
Processor
Memory
wb
29 3
PC
IB 0 1 2 3 4 5 6 7
01234 IR
0000000000
0000000001
000000000
000
Z
Z
A
A
A
B
B
C
Z
Z
Z
XXXYYZZZ ZZAAABBC
MAR (29)
MDR
64
read write
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0000000000
14
0000000001
000000000
18
SM – Cycle
Processor
Memory
wb
29 3
PC
IB 0 1 2 3 4 5 6 7
01234 IR
0000000000
0000000001
000000000
010
Z
Z
A
A
A
B
B
C
Z
Z
Z
Z
Z
XXXYYZZZ ZZAAABBC
MAR (29)
MDR
64
read write
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0000000000
14
0000000001
000000000
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Microcode (B) – Instruction Fetch
• Need to copy the correct no of bytes from the Instruction Buffer (IB) to the Instruction Register (IR).
• Use k as the length of the instruction in IB[PC.b] – (ie 1, 2, 3, or 5). – We need to copy this many bytes into the IR.
• PC is the Program Counter (known as IP for Instruction Pointer) fetch.
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for I in 0..k-1 loop
IR[I] := IB[PC.b]
PC := PC + 1 // increments PC.b and carries into PC.w
// current instruction word used to get next word for rest // of (or next) instruction.
ifPC.b =0then
MAR := PC.w
read;
IB := MDR
end if;
end loop;
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SM – Architecture
29 bits
B[0]
B[1]
B[2]
PC 32 bits
length
SP
INSTR
8bits x 8 bytes
Constants
Stack
Label Y:
byte address 8*B[0]+y
Var X:
word – address B[1]+x.w
ie at Mem[B[1]+x.w] Constant 3:
at end of instr space “3” is at [B[0]+”3”.w]
ie Mem[B[0]+”3”.w] = 3
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SM Run-time Environment
• SM has three registers
– b0: Base register 0 points to the instruction area (read only space). – b1: Base register 1 points and accesses a range of addresses from
the top of the stack where local variables of main program are
allocated (stack space). It starts where instruction area is finished. – b2: Base register 2 points and accesses a range of addresses
beneath the main program area. It points to the call-frame of the most recently called procedure/function.
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SM Program – Code and Data
• Program and the data for constants (integer, float, or string) live in Instruction Area.
• Variables in main and functions are allocated in the data area on stack.
• Each program line for SM is 8 bytes (8 integers) long and is composed of
one or more instructions of SM. Program area, thus, consists of
addresses, 10000, 10008, 10016,…
• Each instruction can be 1 byte (ADD, SUB, etc), 2 bytes (LB), 3 bytes
(LH) or (LA, LV) 5 bytes long. Note that that one-byte instructions assume that its operands are available at the top of its runtime environment, i.e., at the top of stack and the one-byte operation like ADD pops two values from the top, adds and pushes the result on the top of stack
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SM Memory Protection Tags
• SM memory is designed with hardware protection.
• Each memory word of 64 bits, carry an extra 4-bit tag (INTG, FLOT, BOOL, STRG, ADDR, INST, etc), which shows its type.
• Once tagged as of one type, can not be used in an operation illegal for that type. For example, MUL (multiplying) will only work if both operands have INTG OR FLOT tag.
• The architecture actually does some type checking for you and traps on miss-use of memory. The tag shows the type of item for that word.
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SM Addressing Modes • Immediate-Mode
LB 3 // push 8-bits, sign extended to 64 as Integer LH 0 3 // push 16-bits, sign extended to 64 as Integer
• Indexed Addressing LA 1, 8
– Load (push) the address b1 + 8
• Indexed Indirect Addressing
LV 1, 8
– Load (push) the value at address b1 + 8
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Assembly Level Instructions (1)
• 0-Address instructions are 1 byte,
• ADD, MUL, AND, OR, XOR [commutative instructions] – Pop 2 entries, perform op and push the result.
• SUB – Pop 2 entries, subtract top from second top entry and push result.
• DIV – Pop 2 entries, divide second top entry by first and push result. (sim for REM – remainder, and POW power of)
• CHS, NOT, ABS – Pop top entry, do operation and push result.
• LT, LE, EQ, NE, GE, GT
•
– Pop top entry and compare to 0 – Push TRUE if true or FALSE if false.
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Assembly Level Instructions (2)
• L – Load – Pop top entry, get memory contents of that address,
push.
• LB – Load Byte – Fetch next instruction byte, sign extend to 64 bits and push onto stack as type INTG
• LH – Load Half-Word – Fetch next 2 instruction bytes, sign extend to 64 `bits, and push onto stack as type INTG
• NOTE: LB, and LH only works for integer not for real. For real you need to use constants.
• DUP – Duplicate the top of stack entry
• ST – Store – Pop 2 entries, store the value at TOS into the at
address given by second.
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The LA/LV Instructions
• LA instruction has the form LA i, x and means Load Address
• LV instruction has the form LV i, x and means Load Value
• They are actually families of instructions, with i being a base register number (0/1/2) which is added to the basic LA/LV opcode.
– LAi:90,91,92
– LVi:80,81,82
• x is a 32 bit offset that is stored in the 4 bytes following the LA/LV opcode. Note that memory is only 32 bits so we can completely reach all memory in any LA/LV instruction.
• LA i,x will compute the value 8*B[I] + x (zero filled to 64 bits) and push
this address onto the stack. LV i,x uses this address to go and fetch
the value of the actual data item.
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Variable Allocation
• ALLOC – Pop top entry, multiply it by 8 and add to Stack Ptr.
• The compiler allocates addresses relative to the start of the Stack area. This gives each its own “varname”.w offset.
• Variables are actually allocated on the stack at the start of program execution, using ALLOC to move the SP. Each is then accessed using a different var.w offset from base registers B[1] (& B[2]).
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Variable Allocation
Eg: U: integer, V: integer, W : integer; // Compiler allocates offsets 0,8,16
LB 3 // Load value of constant, “3” is the offset ALLOC // Move SP by 3 words
U will be at B[1]+0, V at B[1]+8, W at B[1]+16 (access via 1, 0/8/16)
•
LA 1, 0 // opcode for LA 1 is 91 STEP is a special (no operand) form of ALLOC for a single word
B[1] B[1] SP SP
Stack (before allocation)
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Stack (after allocation)
U’s offset 0 V’s offset 8 W’s offset 16
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Variable Access
Read an integer and store it in variable V
B[1] SP
U’s offset 0 V’s offset 8 W’s offset 16
• • •
ST: Store value (first) popped at address popped (second) READI: input integer value, push to stack
LA BaseRegNo, Offset: load address
10008
9
10008
B[1] (1000)
LA 1, 8 READI ST
U B[1]
V (1000)
91 0 0 0 8 61
43
U B[1]
V (1000)
U B[1]
V (1000)
Stack (after allocation)
U V
9
SP W W WSP W SP
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SP
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SM Constants
• Integer constants
– no. of constants,
– followed by each in a separate line. – If absent, just 0
• Floating point constants
– no. of constants,
– followed by each in a separate line. – If absent, just 0
• String constants
– no. of words,
B[0]
INSTR
code
Constants
– followed by each string a null character
– Not necessary to word-fill each string except the
last
– If absent, just 0
• How do you access constants? 14/09/2021
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SM Constants
10
80 0 0 0 80 52 91 0
0 0 96 80 0 0 0 104 80 0 0 096115191 0 0 088614381 0 0 0 96 62 81 0 0 0 8862656581 0 0 0
88626590 0 0 0114 6380 0 0 0886265 0 0232425262728 71 70 72 11 0 0 0 0
4 17 12 15 3 0 2
49 50 65 66 67 68 69 00 53 54 55 71 72 73 00 00
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SM Branch Instructions
• BR: Branch – Pop top entry, load the address into
the PC.
B[0]
INSTR
code
Constants
• BT, BF: Branch True/False – Pop top 2 entries, if top is true/false then load the second entry into the PC.
– In BT if the top entry is not True then nothing happens except TOS changes (same for BF).
• How do you know the branch address?
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SM – Arrays
• Arrays are supported and protected by array descriptors in SM. – This is actually done using tagged memory.
• Access to elements of an array carries hardware support for “index out of
bounds checking”
Array Descriptor
tag 4 bits
size 32 bits
start addr 32 bits
• Compiler only needs to know about the array descriptor for generating array related instructions.
• Array elements (the array body) are initially allocated using the UNDF (undefined) tag, so that they must also be initialized before they are used.
• Note that an array descriptor does not specify the type of values that are to be
stored into the array itself, so an array may contain Integer or Float or Boolean
values (or even a mixture of the three)
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So memory is actually 68 bits wide
35
SM – Arrays
… …
arrays
a1 : X, a2 : Y … …
i: integer, j: integer, k: integer … …
B[1] (1000)
SP
a1 [1, 0] a2 [1, 8]
i [1, 16] j [1, 24] k [1, 32]
Size
Start Add
Size
Start Add
j
…… …
…… …
B[1] (1000)
a1 [1, 0] a2 [1, 8]
i [1, 16] [1, 24]
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SP k [1, 32]
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Instructions for Arrays
• INDEX – Pop 2, form the address of an array element from element no
given by 1st, and the array descriptor which is the second.
• SIZE – gets the size of the array from the descriptor
• ARRAY – Construct descriptor and step SP by size
• ALLOC –
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Accessing Arrays
Syntax Tree
arr
asgn
LV 1,x LV 1,m INDEX LV 1,y LV 1,n INDEX L
LV 0,”2” DIV
ST
// Descriptor Value // M’s value
// Address of X[M] // Descriptor Value // N’s value
// Address of Y[N] // Value of Y[N]
// Value of const 2 // Divide Y[N] by 2. // Store ans at X[M]
X[M] := Y[N] / 2;
div
XM
YN
2
arr
• •
x, y, m, n refer to the offsets from Base Reg 1, of the word where the associated variables X, Y, M, and N are stored.
“2” is the offset from Base Register 0, where the constant 2 is stored.
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Array Allocation
• ARRAY – Pop 2 entries, form an array descriptor from the current value of the SP and the array size which is first popped item, store the descriptor at the address given by the second popped item, move the Stack Pointer by the array size.
• To allocate an array, we first need to allocate space for the descriptor (using ALLOC just like a normal variable).
• When the program starts executing, after allocating actual storage for all the variables and array descriptors, we need to use ARRAY to set up the value of the array descriptor, and to actually allocate the body of each array.
• We need a ARRAY instruction set for each array.
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Array Allocation ……(cont)
• Since we don’t actually allocate the array body until runtime, all we need to know is that there IS an array, we don’t actually need to know how big the array is until we actually execute the ARRAY instruction. So this architecture makes it easy to have dynamically allocated arrays.
• Since the array is supported by a descriptor containing the size, the architecture will also automatically check array bounds and trap on an out-of-bounds error (when INDEX is executed).
• Other traps will occur if “L” is executed and the top of stack item is not an address, or if “ADD” is executed and either of the top 2 items is not arithmetic, if you try to execute from memory that is not tagged as instruction, or try to store into instruction space.
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Array Allocation – example
Example: X[100], Y[100] : integer array; // declare 2 int arrays.
Syntax Tree for X[100] : integer array;
arrdecl
// value of const
// space X,Y desc
// addr X desc spot // value of const 100
LV0, “2”
ALLOC
LA1, x
LV0, “100”
ARRAY
LA1, y
LV0, “100” // value of const 100 ARRAY // set desc for y
// set desc for x
// addr Y desc spot
What will the stack look like after these instructions?
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X
100
41
What does the Stack look like?
100
100
Array body of X
Array body ofY
X: Y:
•The array descriptors each have 100 stored in the top 32 bits and the start address of the array body stored in the bottom 32 bits.
•The actual value stored at X: 100*232 +
start address of X body (with the tag set to DESC).
SP
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DESC DESC
Procedure Activation and Lifetime
• A procedure is activated when called
• The lifetime of an activation of a procedure is the sequence of steps between the first and last steps in the execution of the procedure body
• A procedure is recursive if a new activation can begin before an earlier activation of the same procedure has ended
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Procedure Activations
program sort(input, output)
var a : array [0..10] of integer; procedure readarray;
var i : integer;
begin
for i := 1 to 9 do read(a[i]) end;
Activations:
begin sort
enter readarray leave readarray enter quicksort(1,9)
function partition(y, z : integer) : integer
var i, j, x, v : integer;
begin …
end enter partition(1,9)
procedure quicksort(m, n : integer); var i : integer;
begin
if (n > m) then begin
i := partition(m, n);
quicksort(m, i – 1);
quicksort(i + 1, n)
leave partition(1,9) enter quicksort(1,3) …
leave quicksort(1,3) enter quicksort(5,9) …
end leave quicksort(5,9)
end; begin
a[0] := -9999; a[10] := 9999;
readarray; 14/09/2021 quicksort(1, 9)
leave quicksort(1,9) end sort.
end.
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Activation Trees
s q(1,9)
r
p(1,9) q(1,3)
p(1,3) q(1,0) q(2,3)
q(5,9)
p(5,9) q(5,5) q(7,9)
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p(2,3) q(2,1) q(3,3) p(7,9) q(7,7) q(9,9)
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Control Stack
Activation tree:
Control stack:
Activations:
begin sort
enter readarray leave readarray enter quicksort(1,9) enter partition(1,9) leave partition(1,9) enter quicksort(1,3) enter partition(1,3) leave partition(1,3) enter quicksort(1,0) leave quicksort(1,0) enter quicksort(2,3) …
s q(1,9)
p(1,9) q(1,3)
p(1,3) q(1,0) q(2,3)
s
q(1,9)
q(1,3)
q(2,3)
r
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SM Support for Subprogram Calling
• SM has hardware support for functions and procedures via a call frame that is set up when a sub-program is called
• RVAL is the instruction used to set up the return value of a function
• RETN is the “return from subprogram” instruction
• JS2 sets up the call frame (MSCW – Control Word) for the procedure call, holding the return address, a saved copy of the frame pointer register (called Base Register 2), and the number of parameters that have been passed to the subprogram
• The caller is expected to have set up the function return value location (if required), and to have set up the parameters prior to issuing the JS2 instruction.
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Setting Up The Call Frame
• Before JS2 instruction
previous call frame
…….
Allocated For return value
param n
…….
param 2
param 1
# params (n)
Address of Proc/Func
if required
Base Reg 2
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Subprogram Call Frame
• After JS2 instruction
Return value If required
param n
…….
param 2
param 1
Individual params are accessed via negative offsets from Base Reg 2
Base Reg 2
Saved BR2 return addr
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# params (n)
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Other Instructions
• HALT
• NO-OP
• TRAP
• ZERO
• FALSE
• TRUE
• TYPE
• ITYPE
• FTYPE
• READI
• READF
• VALPR
• STRPR
• CHRPR
• SPACE
• NEWLN
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Stops the program currently running.
Do nothing – for fixing m/c code manually. Stops the program – effectively an Abort.
Integer Zero to TOS Boolean False to TOS Boolean True to TOS
Toggle the arithmetic type on TOS Set type of TOS to INTG
Set type of TOS to FLOT
Reads an integer value from standard input onto stack. Reads a floating pt value from standard input onto stack. Prints value to standard output.
Prints string constant, start addr is on the stack
Prints single character, addr is on the stack Prints a space character
Prints an end-of-line to standard output.
COMP3290 – Semester 2 – 2021 | www.newcastle.edu.au
50
The CD / SM Runtime System
Items Definition
Scanner
Source Code
COMP3290 – Semester 2 – 2021 | www.newcastle.edu.au
Machine Language Definition
Grammar
Parser
Actual machine language
Object Code
Code Generator
Data Simulator Results
Symbol Table
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lexemes
Syntax Tree
